`timescale is an important compiler directive in Verilog. It is written at the beginning of each module. The directive is used to specify the unit and precision used for simulation of the delay time specified in the verilog specification.
Syntax:
`timescale <time_unit> / <precision>
time_unit : This value specifies the unit of time for the delays used in the verilog code
For example, for a design with specification `timescale 10ns/1ns, a delay #100 is interpreted as a delay of 100*10ns = 1000ns
precision : It specifies the precision to which the delays are rounded off.
For example, in a design with specification `timescale 1ns/1ps, the minimum delay of 1ps will be considered for simulation. Any delay smaller than that will be rounded off to the greatest valid value less than that. In this example,
The valid units for timescale specification are s, ms, us, ns, ps and fs (femto-second).
For example, for a design with specification `timescale 10ns/1ns, a delay #100 is interpreted as a delay of 100*10ns = 1000ns
precision : It specifies the precision to which the delays are rounded off.
For example, in a design with specification `timescale 1ns/1ps, the minimum delay of 1ps will be considered for simulation. Any delay smaller than that will be rounded off to the greatest valid value less than that. In this example,
- #1.001 is considered as a valid delay
- #1.0009 will be rounded off to 1ns, since 0.0009ns < 1ps
The valid units for timescale specification are s, ms, us, ns, ps and fs (femto-second).
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